Perl 6 - the future is here, just unevenly distributed

IRC log for #moarvm, 2015-10-19

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01:48 Topic for #moarvm is now https://github.com/moarvm/moarvm | IRC logs at  http://irclog.perlgeek.de/moarvm/today
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09:36 brrt \o
09:37 nwc10 o/
09:37 nwc10 brrt: http://morepypy.blogspot.co.at/2015/10/powerpc-backend-for-jit.html
09:37 nwc10 URL says enough :-)
09:38 nwc10 also, https://gcc.gnu.org/wiki/CompileFarm now has aarch64
09:38 nwc10 and we build fine on it
09:38 nwc10 but, page imples that IBM paid for Power
09:38 nwc10 so, grant application to IBM soon? :-)
09:39 timotimo i hope our jit will reach speedups of 50x at some point ...
09:39 timotimo for things bigger than an empty loop :)
09:46 brrt oh, let's see
09:46 brrt cool stuff
09:47 brrt i'll have to write a 'porting' document
09:47 brrt one day or another
09:47 brrt i have a new topic for a talk at some conference in the future
09:47 brrt 'how to make a JIT on the cheap' or 'how to make building a JIT so simple it can be done in < 1 person-year'
09:47 timotimo hah
09:48 brrt but, cool progress for pypy :-)
09:49 brrt i have a decent guess as to why the performance gain on powerpc exceeds that of the relative gain on x86_64
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09:49 brrt a): x86_64 these days have impressively good branch prediction, and that helps the interpreter
09:50 brrt b): 9.3 to 9.7 is noise, when we're considering we're talking about an average *factor*
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09:51 brrt (i'm not sure, because i haven't calculated it, whether that is calculated as a geometric average, but let's ignore that for now)
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09:52 timotimo it says geometric average
09:52 timotimo under that table, they also say the thing about branch prediction
09:53 brrt aha
09:53 brrt c): powerpc, being a RISC architecture, is 'easier' to write a good code generator for
10:00 brrt oh, i fixed a few bugs on the bus here... but i have a question for you to ponder
10:01 brrt it so happens that i sometimes load a 1-or-2 byte value from memory, and then try to use it as a 4 or 8 byte value
10:01 brrt however, x86 does not clear the upper bytes of a register if you load it word or byte mode
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10:07 Ven_ should it?
10:07 Ven_ don't you have the "zbl" variants for that?
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11:50 brrt actually, you do
11:50 brrt good point
11:55 brrt no, the question is just that when we're loading smaller values and using them as indices, the fact that the higher bytes are not cleared yields a segfault
11:56 brrt my question is really a design question
11:57 brrt should i, when using a smaller-byte value in a larger-byte context - and i know the sizes of my operands, they're encoded througout the expression tree, a): automatically zero-extend all values and not care b): have an explicit 'scale' node to do so
11:58 brrt and b.a): should i explicitly insert it everywhere or b.b): should this be done automatically, and b.b.b: if that is the case, how do i know ahead of time which operations are signed and unsigend
12:00 brrt always design questions :-)
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19:25 konobi jnthn: ping
19:28 TimToady on his honeymoon this week
19:29 konobi ah yes
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