Perl 6 - the future is here, just unevenly distributed

IRC log for #moarvm, 2017-01-19

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02:48 Topic for #moarvm is now https://github.com/moarvm/moarvm | IRC logs at  http://irclog.perlgeek.de/moarvm/today
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07:16 brrt good * #moarvm
07:17 timotimo good good
07:20 brrt ohai timotimo
07:20 brrt i've better news than before
07:20 brrt hmmm
07:20 brrt no scrap that
07:20 brrt okay it's still better news
07:23 brrt so i figured out that i know exactly when a tiles values are fully defined, and that 's prior to the allocation of a new register for a live range that starts afterwards
07:23 brrt (i'm thinking  of a solution for the two-operand-form-problem that doesn't involve me reserving a register)
07:25 brrt i'm probably not going to implement that just yet because resserving a registe ris sooo much easier
07:25 brrt *register
07:25 timotimo yeah, i'd go with the easier route, too
07:26 timotimo it's potentially easy to change it later on
07:26 * brrt nods
07:26 timotimo whatever gets us towards everybody being able to contribute earlier ;)
07:26 brrt but i feel it's also useful to explore the design space a bit as well
07:26 brrt :-)
07:26 timotimo that's also true
07:28 brrt commutative, is the word i'm looking for
07:28 brrt binary operations like ADD, OR, AND, MUL, they are commutative
07:29 brrt others like SUB,XOR,LEFTSHIFT,RIGHTSHIFT, they're not
07:29 timotimo right
07:29 timotimo do we gain a lot from switching the arguments around?
07:30 brrt well, if we don't have to switch the arguments arround, then r0 = r0 <op> r1 the same thing if r0 == r1 and if r0 == r2
07:30 brrt (the same thing as r0 = r1 <op> r2)
07:31 timotimo fair enough
07:32 brrt so in that case, it's never necessary to allocate an extra register
07:32 brrt or to issue a copy
07:33 brrt non-commutative operators, they do have to be copied, because r1 = r1 <op> r2 overwrites r1 (which is invalid), while r2 = r2 <op> r1 is something else
07:33 brrt (this of course is only relevant if r0 == r2)
07:33 timotimo fair enough, yeah
07:40 brrt i have… another solution, yes
07:41 brrt basically; for all live ranges that have a single definition, their only definition is fully defined (registers are completely filled in) at the point of register allocation, because all its dependencies live in earlier live ranges
07:42 brrt so for those cases, i can check a): if it's a direct binary non-commutative operater were' implementing
07:42 brrt b): ensure that r0 != r2 if that is so
07:44 brrt if they have multiple definitions, and some of those are direct non-commutative binary operators, then i can 'split' them off into single-deifnition live-ranges with a *copy* to our current live range
07:44 brrt yes, precious…. *gollum*
07:45 timotimo %)
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07:45 brrt obviously there's a new matter of complexity there
07:45 brrt if i do that, then my current assumption that (two synthetic live ranges are enough for everyone) is no longer enough for everyone
07:48 brrt does… any of this make any sense
07:50 timotimo well, yeah
07:50 timotimo now you need to care about one more register all the time
07:52 brrt well, we have registers, that's not really it…
07:52 brrt hmmm
07:52 timotimo i might have misunderstood or miscommunicated?
07:53 brrt well, it is i who has miscommunicated, if anyone
07:53 brrt please allow me to check
07:53 brrt what do you think is my issue?
07:53 brrt (if you're wrong, it's my mistake, btw :-))
07:54 timotimo well, since we might have to have that extra register to swap around before a two-operand register, that register has to be accounted for, so another live range appears
07:54 timotimo is that not it?
07:56 brrt well, mostly; that's actually the solution i had in mind
07:56 timotimo i'm not sure i'm understanding everything, or if i'm just subconsciously bullshitting my way through our conversations :D
07:57 brrt as long as i believe it :-D
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08:03 timotimo sleep has ended too soon, and instead of feeling energized and lively from getting up early, i feel drained :\
08:05 timotimo maybe i'll try to sleep a little bit more, and then maybe i'll tackle what samcv left for me to do
08:06 brrt sleep well
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08:07 brrt aargh, i've broken the register allocator canary :'-(
08:08 timotimo good thing it's there
08:08 brrt yeah i suppose
08:08 brrt bbl
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14:16 timotimo so ... making shifts work properly is fun
14:16 timotimo there's a function that takes one 16bit piece and spits out three characters into the array you point it at
14:17 timotimo we now need an extra flag that gets communicated to signify "the last of the three was a 'initiate the shift' command" so that the first one in the next bit can properly be interpreted
14:19 timotimo it very much looks like i want to build a little struct like our SerializationReader and Writer structs
14:20 timotimo i think i want to have something like a queue that gets fed the un-tripled 16bit numbers
14:21 timotimo and a following "pipeline stage" would nom single bits out and if there's nothing left it'll ask for a refill
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14:35 * timotimo AFKBBL
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15:03 Geth MoarVM/even-moar-jit: e261922d44 | (Bart Wiegmans)++ | 3 files
15:03 Geth MoarVM/even-moar-jit: Define properties on expression ops
15:03 Geth MoarVM/even-moar-jit:
15:03 Geth MoarVM/even-moar-jit: Flag negation is an expression op property, as is
15:03 Geth MoarVM/even-moar-jit: binary-noncommutativeness.
15:03 Geth MoarVM/even-moar-jit: review: https://github.com/MoarVM/MoarVM/commit/e261922d44
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17:02 timotimo running this errand left me a lot more exhausted than i thought
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17:40 brokenchicken should've walked that errand! :)
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17:58 timotimo clearly
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18:42 timotimo well, my first attempt at running the code i wrote results in tortured screams
18:42 timotimo U+0 'A'
18:42 timotimo U+1 'A'
18:42 timotimo U+2 'A'
18:42 timotimo U+3 'A'
18:42 timotimo U+4 'A'
18:42 timotimo U+5 'A'
18:42 timotimo [...]
18:42 timotimo U+85D02 'A'
18:43 timotimo U+85D03 'A'
18:43 timotimo U+85D04 'A'
18:43 timotimo U+85D05 'A'
18:43 timotimo haha, now it's SPA SPA SPA SPA SPA SPA
18:43 timotimo someone desparately needs some vacation, i see
18:44 diakopter :p
18:45 brokenchicken :)
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18:50 timotimo U+44 'HYPIGNWRITING'
18:50 timotimo U+45 'HENIGNWRITING'
18:50 timotimo U+46 '-MIIGNWRITING'
18:50 timotimo U+47 'NUSIGNWRITING'
18:52 timotimo U+0 'SPACE'
18:52 timotimo U+1 'EXCLAMATION MARK'
18:52 timotimo U+2 ''
18:53 timotimo U+3 'QUOTATION MARK'
18:53 timotimo U+4 'NUMBER SIGNWRITING'
18:53 timotimo that looks good!
18:54 timotimo ah, i know where the empty strings come from at least
18:56 timotimo looks like encoding has an off-by-one for the shift-table
18:56 timotimo such that istead of SIGN it gives SIGNWRITING for the first few codepoints
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19:22 timotimo got it to work it seems like
19:24 timotimo still at least one bug
19:24 timotimo U+74C6 'MARTIAL ARTS UNJ'
19:24 timotimo U+74C7 ''
19:24 timotimo U+74C8 'CROISSANT'
19:24 timotimo is supposed to be MARTIAL ARTS UNIFORM, then CROISSANT
19:24 timotimo but i need really early rest today
19:28 timotimo https://github.com/samcv/UCD/pull/1  -  samcv, you'll get this per mail, too, but i figure i'll guide any sort of discussion into the channel here as well
19:33 timotimo ah i know why UNIFORM gets mangled
19:34 timotimo there's a 40th entry in the shift one table, which is UNIFORM, but it can't be coded properly, because we can only do up to 39 (because we also have 0)
19:34 timotimo sorry, not UNIFORM. it's FORM of course
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19:40 timotimo today:
19:40 timotimo pasting the shift one list into pidgin makes it freeze and consume 100% cpu on one core
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